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KS2508 osd processor for monitor 1 preliminary overview the KS2508 is used to display some characters or symbols on a screen of monitor. basically, the operation is to control the internal memory on chip and generate the r,g,b signals for some characters or symbols. the r,g,b signals are synchro- nized with the horizontal sync. then the r,g,b signals are mixed with the main video signal in the video amp ic. the font data for characters or symbols are stored in the inter- nal rom. this stored data are accessed and controlled by the control data from a micro controller. the control data are trans- mitted through the i 2 c bus. all timing control signals including the system clock are synchronized with the horizontal sync. therefore there is a pll circuitry on chip. features ? 256 rom fonts (each font consists of 12 x 18 dots.) ? full screen memory architecture ? wide range pll available (15 khz ~ 120 khz) ? programmable vertical height of character ? programmable vertical and horizontal positioning ? character color selection up to 16 different colors ? programmable background color (up to 16 colors) ? character blinking, bordering and shadowing ? color blinking ? character scrolling ? fade-in and fade-out ? box drawing ? character sizing up to four times ? 96 mhz pixel frequency from on-chip pll ? iic protocol data transmission (slave address : bah) 16-dip-300 ordering information device package operating temperature KS2508 16-dip-300 0 c ~ 70 c
KS2508 osd processor for monitor 2 preliminary block diagram figure 1. functional block diagram c o n t r o l d a t a 1 6 r a m d a t a 1 6 r o m a d d r 9 d i s p l a y c o n t r o l f o n t d a t a 1 2 c l k h - p u l s e v - p u l s e f r a m e c o n t r o l r o w c o n t r o l h / v / c l k c o n t r o l h / v / c l k c o n t r o l h f l b v f l b v c o _ i n v r e f 1 v r e f v s s _ a v d d _ a v s s _ d v d d _ d s d a s c l i n t r _ o u t g _ o u t b _ o u t f b l k f o n t c o n t r o l d a t a r e c e i v e r c o n t r o l r e g i s t e r s i n g l e c o l o r r o m ( 2 5 6 x 1 8 x 1 2 ) r a m ( 4 8 0 x 1 6 ) d i s p l a y c o n t r o l l e r o u t p u t s t a g e o s d _ p l l t i m i n g c o n t r o l l e r 7 8 6 9 2 3 5 1 4 1 0 1 6 1 5 1 4 1 3 1 2 1 1 f r a m e c o n t r o l r o w c o n t r o l
KS2508 osd processor for monitor 3 preliminary pin configurations figure 2. pin configurations k s 2 5 0 8 v s s - a 1 v c o - i n 2 v r e f 1 3 v d d - a 4 v r e f 5 h f l b 6 s d a 7 s c l 8 v d d _ d 1 6 i n t 1 5 r _ o u t 1 4 g _ o u t 1 3 b _ o u t 1 2 f b l k 1 1 v s s _ d 1 0 v f l b 9
KS2508 osd processor for monitor 4 preliminary pin descriptions table 1. pin descriptions pin no. signal active i/o description 1 vss_a - - ground (analog part) 2 vco_in - input this voltage is generated at the external loop filter and goes into the input stage of the vco. 3 vref1 - input 1.26 v dc voltage from the bandgap reference. connected to ground through a resistor to make internal reference current (typical 36 k w for 27 m a) 4 vdd_a - - +5 v supply voltage for analog part 5 vref - input bandgap reference voltage (typical 1.26 v) 6 hflb low input horizontal flyback signal 7 sda - in/out serial data (i 2 c) 8 scl - in/out serial clock (i 2 c) 9 vflb low input vertical flyback signal 10 vss_d - - ground for digital part 11 fblk - output fast blank signal 12 b_out - output video signal output (b) 13 g_out - output video signal output (g) 14 r_out - output video signal output (r) 15 int - output intensity signal output 16 vdd_d - - +5 v supply voltage for dogital part
KS2508 osd processor for monitor 5 preliminary absolute maximum ratings note: pkg thermal resistance : 64.2 c/w electrical characteristics dc electrical characteristics (ta = 25 c, vdd = 5 v) parameters symbol value unit min. typ. max. maximum supply voltage vdd - - 7.0 v input voltage v i - - 7.0 v operating temperature range t opr -20 - 70 c storage temperature range t stg -40 125 c power dissipation p d - - 1200 mw table 2. dc electrical characteristics parameters (conditions) symbol min. typ. max. unit supply voltage vdd 4.75 5.00 5.25 v supply current (no load on any output) i dd - - 25 ma input voltage v ih 0.8vdd - - v v il - - vss + 0.4 v output voltage (lout = 1ma) v oh 0.8vdd - - v v ol - - vss + 0.4 v input leakage current i il -10 - 10 m a vco input voltage v vco 2.5 v
KS2508 osd processor for monitor 6 preliminary operation timings figure 3. i 2 c bus timing diagram table 3. operation timings parameters (conditions) symbol min. typ. max. unit output signal - r/g/b_out, int, fblk (ta = 25 c v dda = v dd = 5 v , c load = 30pf) rise time t r - - 6 nsec fall time t f - - 6 nsec input signal - hflb, vflb horizontal flyback signal frequency f hflb - - 120 khz vertical flyback signal frequency f vflb - - 200 hz i 2 c interface - sda, scl (refer to figure 3) scl clock frequency f scl - - 300 khz hold time for start condition t hs 500 - - ns set up time for stop condition t sus 500 - - ns low duration of clock t low 400 - - ns high duration of clock t high 400 - - ns hold time for data t hd 0 - - ns set up time for data t sud 500 - - ns time between 2 access t ss 500 - - ns fall time of sda t fsda - - 20 ns rise time of both scl and sda t rsda - - - ns sda scl t hs t sud t ss t hd t high t low
KS2508 osd processor for monitor 7 preliminary functional descriptions data transmission to the KS2508 according to the i 2 c protocol, the KS2508 receives the data from a micro controller. the sda line and the scl line are shown in figure 4. as shown in figure 4, after the starting pulse, the slave address with r/w* bit and an acknowledge are transmitted in sequence, an internal register address of the KS2508 is followed. the first 8-bit byte is the upper 8bits of the register address. the lower 8bits of the register address are followed after the second acknowledge. there is a data transmission format and are two address bit patterns in the KS2508 as following. the slave address of the KS2508 is bah(in hexadecimal). data transmission format row address -> column address -> data byte n -> data byte n+1 -> data byte n+2 -> .... address bit pattern for display registers data (a) row address bit pattern r3 - r0: valid data for row address (b) column address bit pattern c4 - c0: valid data for column address after addressing, data bytes are followed as the above data transmission format. the figure 4 describes the data transmission with the i 2 c bus protocol. figure 4. sda line and scl line (write operation) a15 a14 a13 a12 a11 a10 a9 a8 x x x x r3 r2 r1 r0 a7 a6 a5 a4 a3 a2 a1 a0 x x x c4 c3 c2 c1 c0 sda a5 a4 a3 a2 a1 a0 a6 a7 a9 a8 a10 a11 a12 a13 a14 a15 r/w scl start iic slave address ack msb address ack lsb address ack scl d1 d0 d2 d3 d4 d5 d6 d7 sda d1 d0 d2 d3 d4 d5 d6 d7 ack data byte n(msb data) ack stop ack data byte n(lsb data) d1 d0 d2 d3 d4 d5 d6 d7 data byte n(msb data) ... ...
KS2508 osd processor for monitor 8 preliminary memory map the display ram is addressed with the row and column number in sequence. the display ram consists of four register groups: character & attribute registers, row attribute registers and frame control registers-. as the display area in a monitor screen is 30 columns by 15 rows, the related character & attribute registers are also 30 columns by 15 rows. each register contains a character address and an attribute corresponding to display location on a monitor screen. and one register is composed of 16 bits. the lower 8 bits select characters out of 256 rom fonts. the upper 7 bits are assigned to give a character attribute to a selected font. row attribute registers occupy the 31th column of display ram and provide the row attribute of a blank mode, raster color, raster color intensity, character color intensity, horizontal character size, vertical character size. frame control registers are located at the 16th row. the content of each register is described in figure 5 and fol- lowing register set. figure 5. memory map of display registers 00 01 02 27 28 29 30 character & attribute registers (30 x 15 character display) row 00 row 01 row 13 row 14 row 15 00 01 02 frame control registers row attribute registers
KS2508 osd processor for monitor 9 preliminary rom fonts KS2508 is able to supply 256 single-color rom fonts for describing an osd icon. so a multi-language osd icon can be generated. the standard font $00 is reserved for blank data. figure 6. array of rom fonts $ 0 0 $ 0 1 $ 0 2 $ 0 e $ 0 f $ 1 0 $ 1 1 $ 1 2 $ 1 e $ 1 f $ 2 0 $ 2 1 $ 2 2 $ 2 e $ 2 f $ e 0 $ e 1 $ e 2 $ e e $ e f $ f 0 $ f 1 $ f 2 $ f e $ f f
KS2508 osd processor for monitor 10 preliminary scroll the scrolling function is to display or erase a character slowly from the top line to the bottom. the scrolling time is controlled by 'scrt' bit of the frame control registers. if 'scrt' bit is high, then the time is 0.5 sec. otherwise, 1 sec. character bordering & shadowing bordering shadowing
KS2508 osd processor for monitor 11 preliminary character height control two examples of the height-controlled character are shown in the following figure. the height control is performed by repeating some lines. the repeating line-number comes from the equation below. [# of the repeating lines = 2 + n m ] , where n = 1,2,3,... and m = round{14 ? (ch[5:0]-18)}. if the m value is less than or equal to 1, all the lines of the standard font are repeated once or more. this is described as following. (i) if ch[5:0] is greater than 32, and less than or equal to 46 (32 < ch[5:0] 46), then all lines are repeated once or twice. the lines repeated twice are selected by the following equation. [# of the repeating lines = 2 + n m ] , where n = 1,2,3,... and m= round{14 ? (ch[5:0]-32)}. (ii) if ch[5:0] is greater than 46, and less than or equal to 60 (46 < ch[5:0] 60), then all lines are repeated twice or three times. the lines repeated three times are selected by the following equation. [# of the repeating lines = 2 + n m ] , where n = 1,2,3,... and m= round{14 ? (ch[5:0]-46)}. iii) if ch[5:0] is greater than 60, and less than or equal to 64 (60 < ch[5:0] 64), then all lines are repeated three or four times. the lines repeated four times are selected by the following equation. [# of the repeating lines = 2 + n m ] , where n = 1,2,3,... and m= round{14 ? (ch[5:0]-60)}. the repeating line-number is limited to 16.
KS2508 osd processor for monitor 12 preliminary standard font(12*18) standard font(12*18) standard font in high vertical resolution height-controlled font : added line standard font in more higher vertical resolution height-controlled font : added line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
KS2508 osd processor for monitor 13 preliminary frame control & timing figure 7 shows the composition of display frame with the osd characters. figure 7. frame composition with the osd characters user can determine the dot frequency by the equation of h freq. x the number of horizontal resolution. and the number of horizontal resolution is determined by the bit9 - 8 (dot 1,dot 0) of the frame control registers-1. if dot 0 = ?0?, dot 1 = ?0?, then the dot frequency is calculated by the equation of h freq. 320. if the h freq. = 15 khz, then the dot frequency is 15 khz 320 = 4.8 mhz. if dot 0 = ?1?, dot 1 = ?1? and the horizontal frequency is 120 khz, then the dot frequency is 120 khz 800 = 96 mhz. 96 mhz is the maximum clock frequency in this processor. 30 columns(=30 x 12 dots) 15 rows(15 x 18 dots) background screen osd characters hflb hp[7:0] vp[7:0]
KS2508 osd processor for monitor 14 preliminary register description ?? c h a r a c t e r & a t t r i b u t e r e g i s t e r : r o w 0 0 ~ 1 4 , c o l u m n 0 0 ~ 2 9 f e d c b a 9 8 7 6 5 4 3 2 1 0 b i n v b o x 1 b o x 0 b g r b l i n k - c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c h a r a c t e r a t t r i b u t e c h a r a c t e r c o d e 2 5 6 f o n t s ) ?? r o w a t t r i b u t e r e g i s t e r : r o w 0 0 ~ 1 4 , c o l u m n 3 0 f e d c b a 9 8 7 6 5 4 3 2 1 0 - b r e n i n t e c b l i b o x e b o r d s h a r b r g r r r i n t c i n t h z 1 h z 0 v z 1 v z 0 r a s t e r c o l o r i n t e n s i t y c h a r a c t e r s i z e ?? f r a m e c o n t r o l r e g i s t e r 0 : r o w 1 5 , c o l u m n 0 0 f e d c b a 9 8 7 6 5 4 3 2 1 0 - f d e f d e t v p o l h p o l - - - - e r a s e e n s c r i s c r t b l i 1 b l i 0 b l i t ?? f r a m e c o n t r o l r e g i s t e r 1 : r o w 1 5 , c o l u m n 0 1 f e d c b a 9 8 7 6 5 4 3 2 1 0 c p 1 c p 0 f p l l h f 2 h f 1 h f 0 d o t 1 d o t 0 - f b l k c h 5 c h 4 c h 3 c h 2 c h 1 c h 0 p l l c o n t r o l c h a r a c t e r h e i g h t c o n t r o l ?? f r a m e c o n t r o l r e g i s t e r 2 : r o w 1 5 , c o l u m n 0 2 f e d c b a 9 8 7 6 5 4 3 2 1 0 h p 7 h p 6 h p 5 h p 4 h p 3 h p 2 h p 1 h p 0 v p 7 v p 6 v p 5 v p 4 v p 3 v p 2 v p 1 v p 0 h o r i z o n t a l s t a r t p o s i t i o n v e r t i c a l s t a r t p o s i t i o n
KS2508 osd processor for monitor 15 preliminary table 4. register description registers bits description character & attribute register (row 00~14, column 00~29) c7~c0 (bit 7~0) character code address of 256 rom fonts. blink/fint (bit 9) character blinking/font intensity enable. if ?inte? bit is low, this bit control blinking effect. the blinking period is set by the 'blit' bit and the duty is selected by the 'bli0' and ' bli1' bits. if ?inte? bit is high, this bit control the font intensity combined with ?inte?, ?rint? and ?cint? as following table. b,g,r (bit c~a) character color is determined by these bits. 8 colors can be selected and the color intensity of a character is given by 'cint' bit of row attribute regisers. so user can select up to 16 colors. box 1, box0 (bit e, d) character box drawing. the combinations of this two bits generate four different box drawing modes as following. the following example is the case that box dawing is activated with the font 'a' * bit f~d(rb/rg/rr) is also used for raster color by setting the 'boxe' bit low. if the 'boxe' bit is low,raster color of a font is determined by this bits . priority of raster color selected here is higher than that of row attribute. binv (bit f) box inversion. the box drawing activated by the bit e and d is changed to white box from black and conversely. inte blink/fint rint cint function 0 0 - - normal 0 1 - - blink 1 0 - - normal(no intensity) 1 1 0 1 character intensity 1 1 1 0 raster intensity 1 1 1 1 character & raster intensity box0 box1 a a a 0 1 0 1 box off
KS2508 osd processor for monitor 16 preliminary row attribute register (row 00 ~ 14, column 30) vz1,vz0 (bit 1, 0) vertical character size control. vertical character size is determined by the combinations of this two bits as following table. hz1,hz0 (bit 3, 2) horizontal character size control. the horizontal character size is determined by the combinations of this two bits as following table. cint (bit 4) character color intensity. if ?inte? bit and this bit is set, the color intensity of characters setting ?fint? bit in the same row is high. rint (bit 5) raster color intensity. if ?inte? bit and this bit is set, the color intensity of rasters setting ?fint? bit in the same row is high. rb,rg,rr ( bit 8~6 ) raster color is determined by these bits. 8 colors can be selected and the color intensity of a character is given by ?rint? bit of row attribute registers. so it can be selected up to 16 colors. sha character shadowing. set this bit to activate characters shadowing. bord character bordering. set this bit to activate characters shadowing. boxe (bit b) box enable. if this bit is set, bit f-d in the character & attribute registers are used for the box-drawing function. otherwise,those are used for raster color of a font. even though the raster color attribute is given by bit 8-6 in the row attribute registers, the priority of bit f-d in the character & attribute registers is higher. cbli (bit c) color blink enable. if this bit is high, color blinking effect is activated. the effect is to repeat color inversion between character and raster. color blinking time and the duty is controlled by bil t, bil 1 and bli 0. inte (bit d) intensity enable. if this bit is set, the function of rint and cint bit are enabled and the bit 9 of character & attribute register control the font intensity effect. otherwise, all intensity functions are disabled and the bit 9 of charac- ter & attribute register control the blinking effect. bren (bit e) back raster blank enable. if this bit is high and the raster color is black, the raster is transparent bit f reserved table 4. register description (continued) registers bits description vz1 vz0 vertical character size 0 0 1x 0 1 2x 1 0 3x 1 1 4x hz1 hz0 horizontal character size 0 0 1x 0 1 2x 1 0 3x 1 1 4x
KS2508 osd processor for monitor 17 preliminary frame control register 0 (row 15, column 00) bli t (bit 0) blink time control. if this bit is high, the blink time is 0.5 sec. otherwise, 1 sec. bli 1,bli 0 (bit 2,1) blinking duty control. the blinking duty is controlled by the combination of this two bits as following. scrt (bit 3) scroll time control. if this bit is high, the scroll time is 0.5 sec. otherwise, 1 sec. scrl (bit 4) scroll enable. the scroll display is activated by setting this bit high. en (bit 5) osd enable. if this bit is high, osd is enable. otherwise, disable. erase (bit 6) ram erasing. ram data are erased by setting this bit. bit a ~ 7 reserved. hpol (bit b) polarity of horizontal fly back signal. positive 1, negative 0 vpol (bit c) polarity of vertical fly back signal. positive 1, negative 0 fdet (bit d) fade-in and fade-out time control. if this bit is high, the time is 0.5 sec. otherwise, 1 sec. fde (bit e) fade-in and fade-out enable. the fade-in and fade-out effect is activated by setting this bit high. bit f reserved. table 4. register description (continued) registers bits description bli 1 bli 0 blinking duty 0 0 blink off 0 1 duty 25% 1 0 duty 50% 1 1 duty 75%
KS2508 osd processor for monitor 18 preliminary frame control register 1 (row 15, column 01) ch 5~ch 0 (bit 5~0) character height control. the vertical character size is determined by the bit 'vz1' and vz0'. according to the value made by this six bits, the character height is determined. if the value is 32, the number of vertical pixel of character font is 32. eventually, the character height is expanded from 18 to 63. the binary vlaue must be greater than 18. fblk (bit 6) it determines the configuration of fblk output pin. when it is clear, fblk pin outputs high during displaying characters or rasters. otherwise,fblk pin outputs high only during displaying characters. dot 1,dot 0 (bit 9,8) this two bits determine the number of dots per horizontal line. hf 2~hf 0 (bit c~a) the horizontal frequency information is transferred by this three bits. fpll (bit d) if this bit is high, the vco block of osd_pll operates on full range (4mhz - 96 mhz). cp 1,cp 0 (bit f,e) this bit controls charge pump output current. table 4. register description (continued) registers bits description dot 1 dot 0 no. of dots 0 0 320 dots/line 0 1 480 dots/line 1 0 640 dots/line 1 1 800 dots/line hf2 hf1 hf0 hf information 0 0 0 15 khz < hf < 20 khz 0 0 1 20 khz hf <35 khz 0 1 0 35 khz hf < 50 khz 0 1 1 50 khz hf < 65 khz 1 0 0 65 khz hf <80 khz 1 0 1 80 khz hf < 95 khz 1 1 0 95 khz hf < 110 khz 1 1 1 110 khz hf < 120 khz cp 1 cp 0 charge pump current 0 0 0.5ma 0 1 0.75ma 1 0 1.0ma 1 1 1.25ma
KS2508 osd processor for monitor 19 preliminary frame control register 2 (row 15, column 02) vp 7~vp 0 (bit 7~0) vertical start position control. it means the top margin height from the v-sync reference edge. ( = vp[7:0] 4 ) hp 7~hp 0 (bit f~8) horizontal start position control. it means the horizontal display delay from the h-sync reference edge to the 1'st pixel position of characters. ( = hp[7:0] 6 ) table 4. register description (continued) registers bits description
KS2508 osd processor for monitor 20 preliminary standard rom fonts
KS2508 osd processor for monitor 21 preliminary
KS2508 osd processor for monitor 22 preliminary application circuit 101 5.6k 36k 4.7k 104 vcc=5v 1 2 sda scl 2k 2k + 4.7uf r_out g_out b_out fblk int bead 1uh + 100uf 104 4.7k + 100uf 104 6.2k 392 vcc 470 2n3904 vcc 120 102 120 400 400 400 400 400 120 2.2nf hflb vflb vdd_d 16 r_out 14 g_out 13 b_out 12 fblk 11 int 15 vflb 9 vss_d 10 vss_a 1 vco_in 2 vref1 3 vdd_a 4 vref 5 hflb 6 sda 7 scl 8 KS2508 + 100uf 104

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